- Heterogeneous integration combines different chips and materials into a single system, overcoming the limitations of the classic monolithic approach.
- Techniques such as 3D NAND, monolithic stacking, interposers and hybrid bonding allow for increased density, performance and energy efficiency.
- Key applications include high-performance computing, automotive, IoT, medical devices, and embedded photonics, both classical and quantum.
- The main challenges are thermal management, material compatibility and cost, addressed through new EDA tools and specialized centers of excellence.
Heterogeneous integration has become the microelectronics industry's key strategy for continued progress as the traditional model of scaling a single monolithic chip reaches its limits. Instead of manufacturing everything on a single wafer and at a single node, very different chips, materials, and technologies are combined within a single system, leveraging the best of each and minimizing the distances between functional blocks.
This shift in focus aligns perfectly with the "More than Moore" philosophy : it's not just about cramming more transistors per square millimeter, but about building far more powerful, specialized, and efficient systems by blending optical, mechanical, RF, memory, and advanced logic components into a single package. From 3D NAND flash memory with hundreds of layers to chiplets for data centers, medical devices, and wearables, heterogeneous integration is redefining how semiconductors are designed and manufactured.
What exactly is heterogeneous integration?
When we talk about heterogeneous integration, we're referring to the combination of chips and devices from different technological processes and domains (digital CMOS, RF, power, photonics, MEMS, sensors, etc.) in a single system. Each component is manufactured using the technology that offers the best performance or cost, and then they are interconnected very close to the chip or even stacked in 3D.
In the classic monolithic System-on-Chip (SoC) approach , all functions are integrated onto the same silicon chip and on the same manufacturing process line. This model worked very well for mobile and consumer electronics, provided all parties agreed to share the same technology and the same thermal, voltage, and material constraints. However, as demands increase for higher power outputs, higher frequencies, or highly specialized sensors, these compromises become unacceptable.
With heterogeneous integration, on the other hand, a high-frequency switch can be fabricated on a semiconductor other than general-purpose CMOS , a power block can be built on GaN or a Class III-V device, and an optical sensor can be implemented on a platform optimized for photonics. All of these are integrated at the package or interposer level with extremely high-density interconnects, achieving very short paths and low latencies between blocks.
When the concept is extended to the entire functional set, it is even referred to as hetero system integration : not only are different chips joined together, but the entire system is designed and packaged considering power, cooling, communications, security and reliability from the beginning.
From “More Moore” to “More than Moore”
Since 1965, the industry has been guided by Gordon Moore's famous rule of thumb, according to which the number of transistors on a chip roughly doubles every two years . For decades this has held true thanks to the constant miniaturization of lithography, down to nodes on the order of 5 nm or less.
However, as we approach the physical and economic limits of miniaturization, simply reducing the size of transistors is no longer enough. Today, three major technological trends coexist: the continuation of factory scaling ( “More Moore” ), the explosion of new advanced packaging and heterogeneous integration ( “More than Moore” ), and the emergence of radically different architectures such as neuromorphic computing and quantum computing.
In the field of storage, 3D NAND memory has been an early demonstration of how to leverage the third dimension. Manufacturers have moved from planar NAND to devices that stack vertically in layers of around 200, multiplying density without relying solely on reducing the size of each cell.
In high-performance logic, the prevailing strategy is to break large dies into specialized chiplets , manufacture each one on the most suitable node, and reassemble the system using advanced interconnection: 2D redistribution layers, 2.5D interposers, 3D stacking with TSV, or hybrid bonding, depending on the application. This enables modularity, improved manufacturing yields, and shorter time to market.
Heterogeneous integration is, in essence, the practical way to make "More than Moore" a reality , maximizing functional density and proximity between chips without forcing everyone to use the same node or the same technology.
3D NAND and the challenges of vertical manufacturing
The path to 3D integration began to take shape with the evolution of NAND flash . Thanks to 193 nm immersion lithography and multi-patterning techniques, manufacturers were able to reduce the size of planar NAND to the 1x nm node range, meaning extremely small dimensions for a two-dimensional design.
In classic planar NAND flash memory, horizontal strips of polysilicon are generated that act as wordlines and connect the control gates of each memory cell. The bottleneck arose when the critical element, the floating gate, stopped scaling correctly: the capacitive coupling ratio between the floating gate and the control gate deteriorated, compromising the reliable operation of the cell.
Faced with this limitation, companies like Samsung decided to radically change their approach and invest in 3D NAND . In 2013, they introduced their first commercial V-NAND, a 128 Gbit chip with 24 vertical layers and approximately 2,5 million channels. Later, they introduced 32-layer versions and even SSDs based on these architectures . Other players such as Micron, SK Hynix, and Toshiba followed suit.
In 3D NAND flash memory, the traditional flat polysilicon strips are stretched, bent, and oriented vertically. The floating gate concept is replaced by charge trap technologies based on silicon nitride films, where charge is stored in opposite regions of the same structure. The result is a complex stack of materials and layers that must be manufactured with extremely tight tolerances.
Samsung named its 3D technology Terabit Cell Array Transistor (TCAT) , a gate-all-around architecture in which the gate completely surrounds the channel. This design is implemented with a 30-40 nm process and gate-last flow, further complicating the manufacturing process.
The TCAT process begins with a CMOS substrate onto which layers of silicon nitride and silicon dioxide are deposited alternately. This stacking, which resembles a kind of "layer cake ," represents the first major challenge: the alternating deposition of the stack. Using CVD (Chemical Vapor Deposition), very thin sheets are deposited, requiring high uniformity and very low defect levels, something that becomes even more complex as the goal is to exceed 32 layers.
The number of layers in this initial stack will determine the final number of memory levels in the device. A hard mask is then added to this structure, and holes are drilled using photolithography. Next comes another critical stage: etching trenches with extremely high aspect ratios from the top down to the substrate. These aspect ratios are up to ten times greater than in planar technology, requiring extreme control of the etching process.
After etching, the walls of the hole are lined with polysilicon to form the channel, and the central space is filled with silicon dioxide, creating the so-called " macaroni channel ." Internal columns are then defined using slit etching processes, and the original alternating nitride and oxide layers are removed, so that the final structure resembles a narrow, finned tower.
For the system to function, it is essential to connect the peripheral logic to the control gates of each memory level. This requires an additional, highly complex step: staircase etching , which creates a kind of staircase on one side of the device to electrically access the different layers. This entire set of techniques illustrates the inherent complexity of advanced vertical integration, foreshadowing the challenges posed by heterogeneous integration in other areas.
Technological keys to heterogeneous integration
To bring these complex systems to life, the industry draws on a wide range of technological tools : from hybrid bonding to on-chip network architectures, including organic and glass interposers. The choice of one or another depends on the use case, cost requirements, and desired performance.
At the most basic level (sometimes called level 0), we find the individual chip . At level 1, chips are integrated onto a wafer or stacked on top of each other using TSV, microbumps, or direct bonding. Level 2 typically corresponds to an integration layer based on organic or glass interposers with connections to the rest of the system. Level 3 is occupied by the substrate itself as the system carrier, which can add even more functionality.
Centers of excellence in heterogeneous integration, such as Fraunhofer IZM and its partners, work precisely to master this toolbox and help the industry select the most suitable set of processes for each application: from low-cost fan-out packaging to near-monolithic integration for very high-density computing.
Monolithic 3D integration and Network-on-Chip architectures
One of the key approaches is monolithic 3D integration , which involves stacking several active layers directly onto a single silicon wafer, forming a monolithic vertical structure instead of multiple assembled chips. This technique drastically reduces communication distances between layers and greatly increases interconnect density.
This type of integration relies on very precise control of the thermal budget , as the upper layers are processed only after the lower layers are nearly complete. Therefore, moderate temperatures are used, along with highly accurate alignment markers, to ensure each new layer is positioned exactly where it should be.
In parallel, Network-on-Chip (NoC) architectures have emerged as a response to the problem of how to efficiently move data between an increasing number of cores, memories, and accelerators within a single system. Instead of point-to-point connections and shared buses, a NoC implements a grid network with routers and channels, which allows scaling to very complex systems by reducing bottlenecks.
Integrated with TSVs or silicon vias, these networks are particularly relevant in 3D solutions and platforms with multiple chiplets. A design team can thus optimize information flow , adapting the network topology to the communication pattern of their application, which is critical in artificial intelligence or autonomous driving.
Photonic integration and heterogeneous waveguides
Another key aspect of heterogeneous integration is the incorporation of integrated photonics directly into the same packaging environment or even the same wafer as the electronics. So-called heterogeneous waveguides mix different materials (e.g., silicon and III-V compounds) to guide light with low losses and high speed within a chip.
This type of system is especially valuable in the core region of very high-performance chips, where traditional electrical connections begin to encounter limitations in power consumption and latency. By directing the optical signal through specifically designed cavities and pathways, interference is minimized, and extremely fast data transmission is achieved with significantly lower power consumption.
The ability to combine electronic and optical blocks on a single platform opens the door to applications such as high-performance computing with internal optical links, next-generation data center interconnections, or even the integration of key quantum system components into more compact chips.
Applications: from automotive to IoT and medicine
Heterogeneous integration is a cross-cutting technology that impacts virtually every sector: high-performance computing, automotive, communications, renewable energy, smart agriculture, healthcare, and the Internet of Things, among others. Each area applies the same philosophy but with a very different set of processes and cost priorities.
In high-performance computing and training large AI models, the primary goal is to maximize computational performance per watt and per unit area. This is achieved by combining state-of-the-art GPUs or TPUs with high-bandwidth memory stacks using hybrid bonding or 3D stacking, creating extremely dense modules.
In the medical field, the integration of chiplets allows for highly customized designs: processing blocks, analog signal acquisition, wireless communications, and hardware security can be mixed in very specific configurations for each type of device, from patient monitors to implants and health wearables.
Advanced materials: GaN and III-V semiconductors
The integration of materials such as gallium nitride (GaN) and other III-V group semiconductors, fundamental for power, radio frequency, and high-frequency communications applications, deserves special mention. These materials offer superior performance when handling high voltages, intense currents, or very high-frequency signals.
By integrating them with silicon wafers using silicon vias and hybrid bonding technologies, design teams can obtain devices with improved thermal management and lower power consumption , without sacrificing compatibility with large-scale manufacturing processes. This has already become a de facto standard for certain segments of power electronics and advanced RF systems.
This GaN/III-V/silicon combination fits perfectly into the logic of heterogeneous integration: each material is used only where it adds the most value, and is connected through a packaging infrastructure that ensures short paths, low parasitic inductance, and good dissipation of the generated heat.
Chiplets, wearables and new generations of devices
The chiplet strategy isn't limited to large data center processors. It's also transforming sectors like medical devices and personal consumer electronics, where the ability to mix and match functional blocks opens the door to much deeper customization.
In the healthcare sector, a single vendor can offer a set of certified chiplets (processing, communications, specific sensors, hardware encryption, etc.) and combine them into different packages depending on the end device: a vital signs monitor, a smart patch, or a portable diagnostic device. This shortens development cycles and facilitates IP reuse.
Wearable devices particularly benefit from heterogeneous integration. With the incorporation of post-processed CMOS chips, advanced wafer bonding techniques, and ultra-compact packaging, it is possible to design smartwatches, fitness trackers, or headphones with longer battery life, more sensors, and better connectivity, without increasing (and even reducing) the physical size of the device.
In these contexts, a balance between performance, power consumption, and cost is paramount. It doesn't always make sense to use demanding techniques like hybrid bonding; often, fan-out or microbump integration are preferred , as they require less expensive infrastructure and still offer more than enough density for the type of signal and data rate handled.
Recent advances: CFET, FeFET and quantum photonics
Advances in basic devices also play a vital role in heterogeneous integration. Among these, Complementary FETs (CFETs) stand out , a technology that allows nMOS and pMOS transistors to be stacked on top of each other, radically reducing the footprint and improving energy efficiency.
The adoption of CFET in silicon chips promises smaller, more efficient transistors, maintaining effective internal communication thanks to the extremely precise alignment of the layers. This innovation is key to further compressing logic into smaller volumes, which fits perfectly with the concepts of 3D stacking and advanced packaging.
On the other hand, Ferroelectric FETs (FeFETs) utilize ferroelectric materials capable of maintaining their polarization, resulting in very fast, low-power, non-volatile memories with good data retention. By integrating them into the central and active regions of chips, FeFETs improve both the performance and energy efficiency of architectures that need to store and retrieve large amounts of information with low latency.
In parallel, integrated quantum photonics is establishing itself as a leading application of heterogeneous integration. By processing information in the form of quantum states of light, these systems require a tightly integrated combination of waveguides, sources, detectors, and control circuitry, which is only feasible with the close integration of multiple materials and processes.
In all these cases, the package and the way the elements are connected are as important as the devices themselves, and they rely on techniques such as hybrid bonding, silicon wafers, and the intelligent use of vias and alignment markers.
Technical, material and cost challenges
Despite its enormous advantages, heterogeneous integration presents considerable challenges . One of the main ones is the technical complexity of aligning and connecting very different components in such a small volume without triggering defects or internal mechanical stresses.
Thermal management is another critical point: when combining high-power, high-density blocks, the thermal budget becomes a central design parameter. Poor heat distribution or insufficient dissipation can damage sensitive components or seriously degrade performance, so cooling, material selection, and the package architecture itself must be considered together.
Compatibility between different materials (silicon, III-V compounds, GaN, special glasses, organic polymers, etc.) also presents a challenge. Differences in coefficients of thermal expansion, mechanical properties, or chemical stability can lead to stresses, delamination, or premature failure if not properly managed during design and manufacturing.
Added to all this is the issue of cost and scalability. The most advanced technologies, such as ultra-thin pitch hybrid bonding, require expensive equipment and a highly sophisticated infrastructure, which increases production costs. The major challenge for the industry is finding the balance between performance, cost, and production volume , selecting only the tools truly necessary for each market.
EDA, reliability and the role of research centers
The rise of heterogeneous integration is also forcing electronic design tools (EDA) to evolve . It is no longer enough to describe a single monolithic chip: it is now necessary to model interposers, redistribution layers, TSV, multiple bonding, three-dimensional thermal effects, and electromechanical reliability, among many other factors.
Research centers like Fraunhofer IZM provide key value by making production lines and test benches available to industry for new packaging and integration technologies. In addition to developing processes, they conduct reliability testing that goes beyond mere electrical testing, incorporating the functional behavior of sensors, actuators, and RF interfaces to understand the causes of potential failures.
Historically, research institutes could work with equipment two or three generations behind the state of the art in industry. Today, the pressure from applications such as AI and high-performance computing is forcing them to bring their laboratories closer to the level of top-tier cleanrooms , with the consequent increase in costs and continuous investment in infrastructure.
At the same time, some manufacturers are dedicating entire factories solely to advanced packaging tasks, repurposing node facilities considered “obsolete” for logic manufacturing, but perfectly suitable for producing interposers or high-density interconnection structures. This model fits very well with the idea of maximizing the use of the existing industrial base.
Impact on edge computing, deep learning and sustainability
In the field of edge computing , heterogeneous integration allows processing capacity to be placed very close to where data is generated, reducing the need to send information to the cloud and easing the pressure on networks and data centers. By combining different wafers and functional blocks, devices capable of executing complex tasks on-site are obtained, while maintaining low power consumption and a small footprint.
Deep learning applications require chips with high parallel computing capacity and enormous memory bandwidth. The combination of compute chiplets with stacked memories and optimized NoC networks, along with advanced bonding processes, makes it possible to train and deploy increasingly large models without the cost and power consumption skyrocketing to unsustainable levels.
Sustainability is also a key part of the equation. The underlying idea of heterogeneous integration is to achieve maximum performance and functionality at the lowest possible economic and environmental cost. Initiatives such as the Green ICT projects study the environmental footprint of information and communication infrastructures, from the selection of raw materials and wafer processing to board design and systems integration.
In the realm of hardware security, integrating functions across various distributed blocks, with elements such as RFID micro-tags embedded in refurbished chips, can improve supply chain traceability and reduce single points of failure, thereby strengthening the reliability of critical systems. This is all part of an approach where performance, security, and sustainability go hand in hand.
Taking this whole picture together, heterogeneous integration is emerging as the pillar that will allow microelectronics to continue to move beyond the limits of simple miniaturization, combining very diverse technologies and materials to offer more powerful, efficient systems adapted to the real needs of each application.
